S S Kerur

@sdmcet.ac.in

Assistant Professor SG
SDM College of Engineering and Technology Dharwad

S S Kerur


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https://researchid.co/kerurss

EDUCATION

B.E, M.E, Ph. D

RESEARCH INTERESTS

VLSI architectures, Embedded Systems
15

Scopus Publications

271

Scholar Citations

6

Scholar h-index

5

Scholar i10-index

Scopus Publications

  • Performance Metrics Comparison of 8-Bit Adder Architectures in 45nm CMOS
    Vinayak P Miskin, S S Kerur, Om P Sulakhe, Hanumesh V Shahapur, Anish G Deshpande, et al.
    3rd IEEE International Conference on Networks Multimedia and Information Technology Nmitcon 2025, 2025
  • Design and Analysis of Advanced Multiplier Circuits using 90nm Technology
    16th International Conference on Advances in Computing Control and Telecommunication Technologies Act 2025, 2025
  • 2×VDD IO buffer with 1×VDD devices considering hot-carrier and gate-oxide reliability issues
    Dharmaray Nedalgi, Saroja V. Siddamal, S.S. Kerur
    Integration, 2024
  • Energy efficient routing protocol for enhancing the network lifetime in wireless sensor network
    Veeresh Hiremath, Sidlingappa Kerur, Anand Gudnavar
    Indonesian Journal of Electrical Engineering and Computer Science, 2024
    Wireless sensor networks (WSNs) confront significant challenges related to battery capacity, as sensor nodes operate on limited energy resources. To address this issue, low energy adaptive clustering hierarchy (LEACH) protocol is commonly employed for power management in WSNs. LEACH is commonly used for power management. Here, sensing region is divided into clusters and sectors, placing a gateway node at the center to minimize energy consumption during data transmission. It employs one-hop, two-hop, or three-hop pathways based on node proximity to the base station (BS) to optimize energy usage. Network performance is assessed using rounds, throughput, and energy usage. MATLAB simulations compare the proposed approach with dual layer LEACH (DL-LEACH) and LEACH, showing significant improvements in network lifetime. The proposed scheme outperforms LEACH by 515% and 347% for 20% and 50% node depletion, respectively. Compared to DL-LEACH, it extends network lifetime by 27% and 59% under similar scenarios. Sectoring, clustering, and multi-hop communication reduce energy consumption, enhancing network lifetime and addressing WSN challenges effectively.
  • Performance Analysis of Parallel Prefix Adders using 90nm Technology
    Vinayak P Miskin, S S Kerur, Sumanth Y Kargar, Samarth Joshi, Rahul Dhanesha, et al.
    2024 Global Conference on Communications and Information Technologies Gccit 2024, 2024
    This paper presents a comparative analysis of delay performance in four distinct adder architectures: Brent-Kung, Ladner-Fischer, Han-Carlson, Kogge-Stone, and Ripple Carry Adder. Adders are fundamental components in digital circuits, crucial for efficient arithmetic operations in various computational systems. Each architecture employs unique design strategies to optimize carry propagation, influencing their overall speed and efficiency. The Ripple Carry Adder, with its straightforward sequential design, serves as a baseline for comparison, while the parallel-prefix architectures of Brent-Kung, Ladner-Fischer, Han-Carlson and Kogge-Stone Adders offer advanced solutions for reducing delay and improving Power-Efficiency. Through detailed simulations and analysis using Cadence Virtuoso, the Delay, Power-Efficiency and transistor count characteristics of each adder are evaluated, highlighting their strengths and tradeoffs. This study includes the design, simulation, and performance evaluation of these adder architectures using 90 nanometer technology, aiming to provide a comprehensive comparison that guides the selection of optimal adder designs for high-performance digital applications.
  • An Improved VLSI Architectural Design of Discrete Cosine Transform Based on the Loeffler-DCT Algorithm
    Shrikanth K. Shirakol, S. S. Kerur
    International Journal of Intelligent Engineering and Systems, 2023
    : The Discrete Cosine Transform (DCT) is a basic transform block used in Adaptive Multicore Transform (AMT), which is a core of High Efficiency Video Coding (HEVC) and Versatile Video Coding (VVC) standards. AMT uses artificial intelligence technique to decide on the transform output. The suggested One-Dimensional DCT architecture is conceived by 8-point structure Loeffler-DCT technique and synthesized using a floating-point Arithmetic. By preserving the structural regularity as the Loeffler-based design, the optimized floating-point architecture consumes optimum space and delay thereby increasing the precision. The work focuses on obtaining high precision output without compromising on ADP (Area-Delay-Product). Due to the fact that the floating-point multiplier unit is developed using shift-add operations, the results reveal the accomplishment of better resolution output while maintaining Root Mean Square deviation as low as 0.0062. A total of 117 additions, 66 shifts are employed in the suggested architecture. The proposed 1D-DCT is used as a sub-block in developing the architecture of 2D-DCT using only 50% of the 1D-DCT subblocks that is needed for the conventional technique. The 8 X 8 2-D DCT, is computed using only 8 1-D DCT's and additions, instead of using 16 1-D DCT's, as in the traditional row-column method. The model is tested with standard images, which resulted in better PSNR and MSE compared to the standard method. In comparison to the state-of-the-art on DCT, the proposed method obtains a root mean square error that is negligible up to three decimal places resulting in improvement of PSNR by 17%, with a maximum clock frequency of 496MHz has been achieved. The proposed design strikes a balance between trade-off parameters such as area, speed, and precision.
  • Hardware Implementation and Comparison of OE Routing Algorithm with Extended XY Routing Algorithm for 2D Mesh on Network on Chip
    Radha Velangi, S. S. Kerur
    Lecture Notes in Networks and Systems, 2022
  • An Area-Efficient JK Flip-Flop-Based Phase Detector for Phase Measurement System Based on FPGA
    S. S. Kerur, Veeresh, Shrikanth K. Shirakol
    Lecture Notes in Networks and Systems, 2022
  • Industry linked projects as tools for improving employability of budding engineers
    Journal of Engineering Education Transformations, 2021
  • Machine Learning-Based Implementation of Image Corner Detection Using SVM Algorithm for Biomedical Applications
    Santosh M. Herur, S. S. Kerur, H. C. Hadimani
    Lecture Notes in Electrical Engineering, 2021
  • FPGA-Based Implementation of Digital Filters for Image Denoising
    Shrikanth K. Shirakol, Veerayya Hiremath, S. S. Kerur
    Lecture Notes in Electrical Engineering, 2021
  • Design and analysis of 10-bit, 2 MS/s SAR ADC using nonredundant SAR and split DAC
    Kalmeshwar N. Hosur, Girish V. Attimarad, Harish M. Kittur, Gopalkrishna G. Mane, S. S. Kerur
    Lecture Notes in Electrical Engineering, 2019
  • Design and simulation of low power successive approximation register for A/D converters using 0.18um CMOS technology
    International Journal of Engineering and Technology, 2016
  • Implementation of vedic multiplier in image compression using DCT algorithm
    S. S. Kerur, Prakash Narchi, Harish M Kittur, V. A. Girish
    Proceedings of the IEEE International Caracas Conference on Devices Circuits and Systems ICCDCS, 2014
  • Low power high performance carry select adder
    International Journal of Applied Engineering Research, 2014

RECENT SCHOLAR PUBLICATIONS

  • Performance metrics comparison of 8-Bit adder architectures in 45nm CMOS
    VP Miskin, SS Kerur, OP Sulakhe, HV Shahapur, AG Deshpande, ...
    2025 Third International Conference on Networks, Multimedia and Information … , 2025
    2025
    Citations: 2
  • Performance Analysis of Parallel Prefix Adders using 90nm Technology
    VP Miskin, SS Kerur, SY Kargar, S Joshi, R Dhanesha, S Malgavi
    2024 Global Conference on Communications and Information Technologies (GCCIT … , 2024
    2024
    Citations: 2
  • An Improved VLSI Architectural Design of Discrete Cosine Transform Based on the Loeffler-DCT Algorithm.
    S Shirakol, SS Kerur
    International Journal of Intelligent Engineering & Systems 16 (5) , 2023
    2023
    Citations: 7
  • Architectural Design and Optimization of Distributed Arithmetic based 2-D Discrete Cosine Transform
    S Shirakol, SS Kerur
    ICTACT Journal on Microelectronics 8 (01), 1275-1282 , 2022
    2022
    Citations: 2
  • An Area-Efficient JK Flip-Flop-Based Phase Detector for Phase Measurement System Based on FPGA
    SS Kerur, Veeresh, SK Shirakol
    Innovations in Electronics and Communication Engineering: Proceedings of the … , 2022
    2022
    Citations: 1
  • Algorithm with Extended XY Routing Algorithm for 2D Mesh on Network on Chip
    R Velangi, SS Kerur
    Micro-Electronics and Telecommunication Engineering: Proceedings of 5th … , 2022
    2022
  • Hardware implementation and comparison of OE routing algorithm with extended XY routing algorithm for 2D mesh on network on chip
    R Velangi, SS Kerur
    International Conference on Micro-Electronics and Telecommunication … , 2021
    2021
    Citations: 2
  • Industry linked projects as tools for improving employability of budding engineers
    SS Navalgund, JC Nidagundi, SS Kerur
    Journal of Engineering Education Transformations, 55-63 , 2021
    2021
    Citations: 2
  • FPGA-based implementation of digital filters for image denoising
    SK Shirakol, V Hiremath, SS Kerur
    Smart sensors measurements and instrumentation: select proceedings of CISCON … , 2021
    2021
    Citations: 4
  • Machine Learning-Based Implementation of Image Corner Detection Using SVM Algorithm for Biomedical Applications
    SM Herur, SS Kerur, HC Hadimani
    Nanoelectronics, Circuits and Communication Systems: Proceeding of NCCS 2019 … , 2020
    2020
  • Neural Network Based Implementation of Corner Detection for Biomedical Application in Computer Vision.
    SM Herur, SS Kerur, KN Hosur
    Indian Journal of Public Health Research & Development 11 (3) , 2020
    2020
  • Design and Analysis of 10-bit, 2 MS/s SAR ADC Using Nonredundant SAR and Split DAC
    KN Hosur, GV Attimarad, HM Kittur, GG Mane, SS Kerur
    Proceeding of the Second International Conference on Microelectronics … , 2018
    2018
    Citations: 1
  • Booth Modified RNS Multiplier in RNS to Binary Code Converator Using {2P+ 1 2P, 2p-1}
    SS Kerur, H Kittu
    MR International Journal of Engineering & Technology 6 (2), 27-31 , 2018
    2018
  • DESIGN AND SYNTHESIS OF VEDIC FLOATING POINT MULTIPLIER
    S Gulannanavar, SS Kerur
    International Journal of Research in Management & Social Science, 77 , 2017
    2017
  • Design of High Gain two Stage Amplifier for ADC Applications Using Cadence 180nm Technology
    YK Udara, PS Bellerimath, GG Mane, SS Kerur
    2016
    Citations: 1
  • Design of a High Speed Multiplier by Using Ancient Vedic Mathematics Approach for Digital Arithmetic
    A Kumar, S Kamya
    International Journal of Electrical and Electronics Engineers 8 (2), 244-255 , 2016
    2016
    Citations: 2
  • Design and simulation of low power successive approximation register for A/D converters using 0.18 um CMOS technology
    KN Hosur, GV Attimarad, HM Kittur, SS Kerur
    International Journal of Engineering and Technology (IJET) 8, 0975-4024 , 2016
    2016
    Citations: 12
  • Digital implementation of efficient low-power and compact codec system for portable devices using CADENCE tool
    YK Udara, PS Bellerimath, GG Mane, DSS Kerur
    Bonfring International Journal of Research in Communication Engineering 6 … , 2016
    2016
    Citations: 1
  • Implementation and Analysis of Vedic Multiplier Using Different Adder
    A Jain, A Jain
    2015
  • Implementation of vedic multiplier in image compression using DCT algorithm
    SS Kerur, P Narchi, HM Kittur, VA Girish
    2014 2nd international conference on devices, circuits and systems (ICDCS), 1-6 , 2014
    2014
    Citations: 16

MOST CITED SCHOLAR PUBLICATIONS

  • Implementation of Vedic multiplier for digital signal processing
    SS Kerur, JCN Prakash Narchi, HM Kittur, VA Girish
    International Conference on VLSI, Communication & Instrumentation (ICVCI), 1-6 , 2011
    2011
    Citations: 125
  • Low power high speed 16x16 bit multiplier using vedic mathematics
    RK Bathija, RS Meena, S Sarkar, R Sahu
    International Journal of Computer Applications 59 (6) , 2012
    2012
    Citations: 68
  • A high speed 16* 16 multiplier based on Urdhva Tiryakbhyam Sutra
    BR Raju, DV Satish
    International Journal of Science Engineering and Advance Technology, IJSEAT … , 2013
    2013
    Citations: 17
  • Implementation of vedic multiplier in image compression using DCT algorithm
    SS Kerur, P Narchi, HM Kittur, VA Girish
    2014 2nd international conference on devices, circuits and systems (ICDCS), 1-6 , 2014
    2014
    Citations: 16
  • Design and simulation of low power successive approximation register for A/D converters using 0.18 um CMOS technology
    KN Hosur, GV Attimarad, HM Kittur, SS Kerur
    International Journal of Engineering and Technology (IJET) 8, 0975-4024 , 2016
    2016
    Citations: 12
  • An Improved VLSI Architectural Design of Discrete Cosine Transform Based on the Loeffler-DCT Algorithm.
    S Shirakol, SS Kerur
    International Journal of Intelligent Engineering & Systems 16 (5) , 2023
    2023
    Citations: 7
  • Design and Simulation of Floating Point Pipelined ALU Using HDL and IP Core Generator
    P Itagi Mahi, SS Kerur
    International Journal of Current Engineering and Technology , 2013
    2013
    Citations: 6
  • FPGA-based implementation of digital filters for image denoising
    SK Shirakol, V Hiremath, SS Kerur
    Smart sensors measurements and instrumentation: select proceedings of CISCON … , 2021
    2021
    Citations: 4
  • Performance metrics comparison of 8-Bit adder architectures in 45nm CMOS
    VP Miskin, SS Kerur, OP Sulakhe, HV Shahapur, AG Deshpande, ...
    2025 Third International Conference on Networks, Multimedia and Information … , 2025
    2025
    Citations: 2
  • Performance Analysis of Parallel Prefix Adders using 90nm Technology
    VP Miskin, SS Kerur, SY Kargar, S Joshi, R Dhanesha, S Malgavi
    2024 Global Conference on Communications and Information Technologies (GCCIT … , 2024
    2024
    Citations: 2
  • Architectural Design and Optimization of Distributed Arithmetic based 2-D Discrete Cosine Transform
    S Shirakol, SS Kerur
    ICTACT Journal on Microelectronics 8 (01), 1275-1282 , 2022
    2022
    Citations: 2
  • Hardware implementation and comparison of OE routing algorithm with extended XY routing algorithm for 2D mesh on network on chip
    R Velangi, SS Kerur
    International Conference on Micro-Electronics and Telecommunication … , 2021
    2021
    Citations: 2
  • Industry linked projects as tools for improving employability of budding engineers
    SS Navalgund, JC Nidagundi, SS Kerur
    Journal of Engineering Education Transformations, 55-63 , 2021
    2021
    Citations: 2
  • Design of a High Speed Multiplier by Using Ancient Vedic Mathematics Approach for Digital Arithmetic
    A Kumar, S Kamya
    International Journal of Electrical and Electronics Engineers 8 (2), 244-255 , 2016
    2016
    Citations: 2
  • An Area-Efficient JK Flip-Flop-Based Phase Detector for Phase Measurement System Based on FPGA
    SS Kerur, Veeresh, SK Shirakol
    Innovations in Electronics and Communication Engineering: Proceedings of the … , 2022
    2022
    Citations: 1
  • Design and Analysis of 10-bit, 2 MS/s SAR ADC Using Nonredundant SAR and Split DAC
    KN Hosur, GV Attimarad, HM Kittur, GG Mane, SS Kerur
    Proceeding of the Second International Conference on Microelectronics … , 2018
    2018
    Citations: 1
  • Design of High Gain two Stage Amplifier for ADC Applications Using Cadence 180nm Technology
    YK Udara, PS Bellerimath, GG Mane, SS Kerur
    2016
    Citations: 1
  • Digital implementation of efficient low-power and compact codec system for portable devices using CADENCE tool
    YK Udara, PS Bellerimath, GG Mane, DSS Kerur
    Bonfring International Journal of Research in Communication Engineering 6 … , 2016
    2016
    Citations: 1
  • Algorithm with Extended XY Routing Algorithm for 2D Mesh on Network on Chip
    R Velangi, SS Kerur
    Micro-Electronics and Telecommunication Engineering: Proceedings of 5th … , 2022
    2022
  • Machine Learning-Based Implementation of Image Corner Detection Using SVM Algorithm for Biomedical Applications
    SM Herur, SS Kerur, HC Hadimani
    Nanoelectronics, Circuits and Communication Systems: Proceeding of NCCS 2019 … , 2020
    2020