S S Kerur
@sdmcet.ac.in
Assistant Professor SG
SDM College of Engineering and Technology Dharwad
EDUCATION
B.E, M.E, Ph. D
RESEARCH INTERESTS
VLSI architectures, Embedded Systems
Scopus Publications
Scholar Citations
Scholar h-index
Scholar i10-index
Scopus Publications
Shrikanth K. Shirakol and S. S. Kerur
The Intelligent Networks and Systems Society
: The Discrete Cosine Transform (DCT) is a basic transform block used in Adaptive Multicore Transform (AMT), which is a core of High Efficiency Video Coding (HEVC) and Versatile Video Coding (VVC) standards. AMT uses artificial intelligence technique to decide on the transform output. The suggested One-Dimensional DCT architecture is conceived by 8-point structure Loeffler-DCT technique and synthesized using a floating-point Arithmetic. By preserving the structural regularity as the Loeffler-based design, the optimized floating-point architecture consumes optimum space and delay thereby increasing the precision. The work focuses on obtaining high precision output without compromising on ADP (Area-Delay-Product). Due to the fact that the floating-point multiplier unit is developed using shift-add operations, the results reveal the accomplishment of better resolution output while maintaining Root Mean Square deviation as low as 0.0062. A total of 117 additions, 66 shifts are employed in the suggested architecture. The proposed 1D-DCT is used as a sub-block in developing the architecture of 2D-DCT using only 50% of the 1D-DCT subblocks that is needed for the conventional technique. The 8 X 8 2-D DCT, is computed using only 8 1-D DCT's and additions, instead of using 16 1-D DCT's, as in the traditional row-column method. The model is tested with standard images, which resulted in better PSNR and MSE compared to the standard method. In comparison to the state-of-the-art on DCT, the proposed method obtains a root mean square error that is negligible up to three decimal places resulting in improvement of PSNR by 17%, with a maximum clock frequency of 496MHz has been achieved. The proposed design strikes a balance between trade-off parameters such as area, speed, and precision.
S. S. Kerur, Veeresh, and Shrikanth K. Shirakol
Springer Singapore
Radha Velangi and S. S. Kerur
Springer Nature Singapore
Shrikanth K. Shirakol, Veerayya Hiremath, and S. S. Kerur
Springer Singapore
Santosh M. Herur, S. S. Kerur, and H. C. Hadimani
Springer Singapore
Kalmeshwar N. Hosur, Girish V. Attimarad, Harish M. Kittur, Gopalkrishna G. Mane, and S. S. Kerur
Springer Singapore
S. S. Kerur, Prakash Narchi, Harish M Kittur, and V. A. Girish
IEEE
Digital multipliers are indispensable in the hardware implementation of many important functions such as DCT, IDCT, FFT etc in signal processing. This paper deals with Design and implementation of Vedic Multipler in Image Compression using DCT algorithm. The DCT (Discrete Cosine Transform) performs spatial compression of the data while IDCT performs decompression of the data. Here, matrix multiplication is one of the important step in both the transforms. Hence, to perform these computations, we introduce Vedic multiplier which is based on Urdhava Tiryakbhyam(vertical and crosswise) sutra. In this paper, we have designed DCT algorithm using Verilog and code is written in Xilinx I.S.E 7.1i version, synthesized on Xilinx Synthesis Tool (XST). We retrieved Register Transfer Logic (RTL) and the simulation results are observed on Modelsim 6.0 Simulator. These simulation results were compared with matlab simulation results. From the comparison, we see that DCT using Vedic Multiplier is efficiently implemented and the proposed Vedic multiplier significantly improves the computational speed involved in multiplication operations of the image processing. Hence, Vedic multipliers can find immense use in applications of image processing to save time and area.