Physics Guided Transfer Learning and Explainable AI for Sub-5 nm Negative Capacitance FETs DSS Sam 2026 8th International Conference on Devices, Circuits, and Systems (ICDCS), 1-5 , 2026 2026
Analysis of RF Performance in Negative Capacitance FETs for Low-Power Circuits DSS Sam 2026 8th International Conference on Devices, Circuits, and Systems (ICDCS), 1-5 , 2026 2026
Energy-Efficient High-Frequency Ring VCO in 90nm CMOS with Pseudo-NMOS Split-Load Design J Gnanathickam, G Nivetha, DSS Sam, SP Deborah, JM Livingston 2026 9th International Conference on Intelligent Computing and Control … , 2026 2026
Design of Low-Power 32nm Configurable Serial Peripheral Interface for High-Speed Embedded Applications J Gnanathickam, JM Livingston, DSS Sam 2026 IEEE International Conference for Convergence in Computing Technology … , 2026 2026
An Energy-Efficient Dynamic Latch Comparator Architecture in 0.18-μm CMOS Technology TK Chauhan, S Kummaramsetty, DSS Sam The International Conference on Artificial Intelligence and Smart … , 2026 2026
Design of Low Power Dynamic CMOS Comparator for 10–Bit SAR ADC using 180nm Technology Node A Hembram, DSS Sam 2025 5th International Conference on Emerging Research in Electronics … , 2025 2025
A Novel High-Speed CDMA Architecture with Adaptive Code Management for Fast Data Transfer Applications EA Benita, J Gnanathickam, SP Deborah, DSS Sam, TR Kumar 2025 6th International Conference on Electronics and Sustainable … , 2025 2025
Review on FSO Techniques and Modulation Schemes for a Fiber-FSO Hybrid Optical Communication System based on FPGA RKB Das, SSS Priya, D Shylu IEIE Transactions on Smart Processing & Computing 14 (3), 297-306 , 2025 2025
A New Architecture of 4-Bit Flash ADC with Strong ARM Latch Dynamic Comparator MM Reddy, B Tharun, A Kumar, DSS Sam, G Nivetha 2025 IEEE 5th International Conference on VLSI Systems, Architecture … , 2025 2025
Scalable UART Verification using AHP VIP for Optimal Coverage DS Sam, G Nivetha, K Paramasivam 2025 3rd International Conference on Advancements in Electrical, Electronics … , 2025 2025 Citations: 2
Application of machine learning techniques for churn prediction in the telecom business R Krishna, D Jayanthi, DSS Sam, K Kavitha, NK Maurya, T Benil Results in Engineering 24, 103165 , 2024 2024 Citations: 22
Analysis of nano sheet field effect transistor based on performance under different temperature and doping concentrations for 12 nm device R Krishna, D Jayanthi, DSS Sam, K Kavitha, P Ilanchezhian, B Srujana Micro and Nanostructures 194, 207929 , 2024 2024 Citations: 3
Effect of metallic substrate and rubber elastic materials over passive constrained layer damping on tool vibration during boring process G Lawrance, PS Paul, DS Shylu, DS Ebenezer Jacob Dhas, ... Journal of Low Frequency Noise, Vibration and Active Control 43 (3), 1139-1157 , 2024 2024 Citations: 10
Design and analysis of Two stage op-amp in 180nm CMOS Process V Smrithi, DSS Sam, G Manoj 2024 7th International Conference on Devices, Circuits and Systems (ICDCS … , 2024 2024 Citations: 4
Verification of UART using AHB VIP with Maximum Coverage SP Deborah, DSS Sam, PS Paul, D Jayanthi, AL KS, G Nivetha 2024 7th International Conference on Devices, Circuits and Systems (ICDCS … , 2024 2024 Citations: 3
Differential voltage controlled ring VCO with No feedback loop technique for radio frequency applications DSS Sam, PS Paul, D Jayanthi, G Nivetha 2024 7th International Conference on Devices, Circuits and Systems (ICDCS … , 2024 2024 Citations: 4
A low-power 100MS/s Flash ADC with Thermometer code encoding technique for automotive applications PG Golda, DS Sam, SP Paul, D Jayanthi Przegląd Elektrotechniczny 100 , 2024 2024 Citations: 2
Design of 32-bit RISC V using area efficient multiplier based on homogeneous hybrid adder G Sangeeth, D Jayanthi, K Kavitha, P Ilanchezhian, DSS Sam AIP Conference Proceedings 2901 (1), 080012 , 2023 2023 Citations: 1
Optimizing MRF Foam Damper Parameters Using Artificial Neural Networks and Genetic Algorithms for Improved Damping Force Performance S Sarath, PS Paul, G Lawrance, DSS Sam 2023 4th International Conference on Signal Processing and Communication … , 2023 2023 Citations: 1
Design and Implementation of Low Power Unidirectional Shift Register GC Reddy, CN Reddy, V Bandi, M Sreenivasulu, DS Shylu 2023 4th International Conference on Signal Processing and Communication … , 2023 2023
MOST CITED SCHOLAR PUBLICATIONS
Smart intelligent computing and applications SC Satapathy, V Bhateja, S Das Proceedings of the second international conference on SCI 1 , 2018 2018 Citations: 96
Application of machine learning techniques for churn prediction in the telecom business R Krishna, D Jayanthi, DSS Sam, K Kavitha, NK Maurya, T Benil Results in Engineering 24, 103165 , 2024 2024 Citations: 22
A 1.8 V 22mW 10 bit 165 MSPS Pipelined ADC for video applications DS Shylu, DJ Moni WSEAS Transactions on Circuits and systems 13, 343-355 , 2014 2014 Citations: 21
A novel architecture for 10-bit 40MSPS low power pipelined ADC using a simultaneous capacitor and op-amp sharing technique DSS Sam, DJ Moni, PS Paul, D Nirmal Silicon 14 (9), 4839-4847 , 2022 2022 Citations: 20
Design and power optimization of high-speed pipelined ADC with programmable gain amplifier for wireless receiver applications DS Shylu, DJ Moni, G Nivetha Wireless Personal Communications 90 (2), 657-678 , 2016 2016 Citations: 19
Design of low power dynamic comparator with reduced kickback noise using clocked PMOS technique DSSDS Shylu, DJ Moni Journal of Electrical Engineering 16 (3), 10-10 , 2016 2016 Citations: 16
A low power dynamic comparator for a 12-bit pipelined successive approximation register (SAR) ADC DS Shylu, S Jasmine, DJ Moni 2018 4th International Conference on Devices, Circuits and Systems (ICDCS … , 2018 2018 Citations: 15
Design of Grover’s algorithm over 2, 3 and 4-Qubit systems in quantum programming studio D Jingle, S Sam, M Paul, J Ananth, D Selvaraj International Journal of Electronics and Telecommunications 68 , 2022 2022 Citations: 14
A Novel architecture of a Low Power Folded Cascode OTA in 180nm CMOS process DSS Sam, PS Paul, D Jayanthi 2021 7th International Conference on Advanced Computing and Communication … , 2021 2021 Citations: 13
A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique DSS Sam, PS Paul Circuit World 47 (3), 274-283 , 2021 2021 Citations: 12
Design of a power-efficient Kogge–Stone adder by exploring new OR gate in 45nm CMOS process V John, S Sam, S Radha, PS Paul, J Samuel Circuit World 46 (4), 257-269 , 2020 2020 Citations: 12
Design of low power pass transistor logic based adders for multiplier in 90nm cmos process DSS Sam, G Manoj, D Jayanthi, S Babafakruddin, EGV Shriashwinraja 2023 4th International Conference on Signal Processing and Communication … , 2023 2023 Citations: 11
Malware identification in advanced interconnects on SOC G Sangeeth, D Jayanthi, R Krishna, P Ilanchezhian, DSS Sam 2022 International Virtual Conference on Power Engineering Computing and … , 2022 2022 Citations: 11
Effect of metallic substrate and rubber elastic materials over passive constrained layer damping on tool vibration during boring process G Lawrance, PS Paul, DS Shylu, DS Ebenezer Jacob Dhas, ... Journal of Low Frequency Noise, Vibration and Active Control 43 (3), 1139-1157 , 2024 2024 Citations: 10
Power efficient low latency architecture for decoder: Breaking the ACS bottleneck S Radha, DS Shylu, P Nagabushanam International Journal of Circuit Theory and Applications 47 (9), 1513-1528 , 2019 2019 Citations: 10
Design of 12 Bit 100MS/s Low Power Delta Sigma ADC Using Telescopic Amplifier DS Shylu, JAM Helan, J Moni 2018 4th International Conference on Devices, Circuits and Systems (ICDCS … , 2018 2018 Citations: 9
Design and analysis of a two stage miller compensated op-amp suitable for ADC applications DS Shylu, DJ Moni, B Kooran IJRET: International Journal of Research in Engineering and Technology eissn … , 2014 2014 Citations: 9
Design of highly reusable interface for AHB verification module VT Mahendra, DSS Sam, AJ Hernisha, AJ Atchaya 2022 6th International Conference on Devices, Circuits and Systems (ICDCS … , 2022 2022 Citations: 8
Design of Low Power Dynamic Comparator for SAR ADC AJ Herinsha, DSS Sam, AJ Atchaya 2022 6th International Conference on Devices, Circuits and Systems (ICDCS … , 2022 2022 Citations: 8
Design of 1-V, 12-bit low power incremental delta sigma ADC for CMOS image sensor applications DSS Sam, S Radha, DJ Moni, PS Paul, J Jecintha International Journal of Recent Technology and Engineering (IJRTE) vol 7 … , 2019 2019 Citations: 8
