@karunya.edu
Karunya Institute of Technology & Sciences
Analog VLSI Design,Low Power VLSI Design
Scopus Publications
Scholar Citations
Scholar h-index
Scholar i10-index
Raji Krishna, D. Jayanthi, D.S. Shylu Sam, K. Kavitha, P. Ilanchezhian, and B. Srujana
Elsevier BV
G Lawrance, P Sam Paul, DS Shylu, DS Ebenezer Jacob Dhas, C Dineshkumar, PD Jeyakumar, Solomon Jenoris Muthiya, and Netsanet Ayele Getachew
SAGE Publications
Tool vibration is a key factor that affects surface finish, generates noise, and reduces the tool life during conventional boring because of the excessive overhanging length of the tool holder. The interaction between the dynamics of the machine tool and the boring process led to progressive vibration. The creation of appropriate mechanisms in reducing tool vibration will help manufacturing industries to become more productive. In this research, in order to control vibration in the overhanging boring bar, a passive vibration control method was employed. Constrained layer dampers consist of boring bar, substrate, and elastic materials and it is used to minimize tool vibration produced during boring operation. The investigation utilized computational analysis through the ANSYS Workbench platform, employing key parameters such as the overhanging length of the tool holder (100, 150, and 200 mm), substrate material (aluminum, brass, and copper), and elastic material (Nitrile rubber, Natural rubber, and polyurethane). A comprehensive series of 27-run boring experiments were conducted to assess the impact of the constrained layer damper on tool vibration and cutting properties. The results of the study revealed remarkable improvements in various performance metrics. The constrained layer damper demonstrated an impressive 98% reduction in tool vibration, signifying its efficacy in dampening vibrational forces during the boring operation. Furthermore, a substantial 83% decrease in surface roughness was observed, indicating enhanced machining precision and surface finish. The constrained layer damper also exhibited a noteworthy 97.5% reduction in tool wear, highlighting its ability to significantly prolong tool life under challenging machining conditions.
D. S. Shylu Sam, P. Sam Paul, B. Enoch Mani Deepak, B. Shirley Eva Paul, B. Jayanth, and K. Pavitra Kumar
Springer Science and Business Media LLC
Persiya D
Wydawnictwo SIGMA-NOT, sp. z.o.o.
Smrithi V., D.S.Shylu Sam, and G. Manoj
IEEE
Operational amplifiers are an integral part of an electronic system. Typical uses of the operational amplifier are amplifiers, oscillators, filters and also used in many types of instrumentation circuits. Two stage CMOS op-amp is widely accepted due to its simplicity in design topology and its robustness. The design of op-amps continues to pose a challenge as the supply voltage and transistor channel lengths scale down with each generation of CMOS technologies. Operational amplifier is very high gain differential amplifier with high input impedance and low output impedance. Simulation results shows that the power dissipation, Gain and CMRR of the proposed op-amp is 1.3mW, 60dB and 48.7dB in 180 nm CMOS Process.
Persiya Gnana Golda D., D.S. Shylu Sam, P.Sam Paul, D. Jayanthi, and G. Nivetha
IEEE
The essential parts of such as phase-locked loops, signal generators, and signal processors are oscillators. VCOs need to be carefully designed because they operate in the high-frequency range and use the highest amount of power. A very wide output frequency range of 0.029 GHz to 12.89 GHz is demonstrated by the operation outcomes of the proposed VCO, which has been implemented in 90 nm CMOS technology. Its phase noise is — 43.38 dBc/Hz @ 1MHz offset and its power utilisation ranges from 0.0037 mW to 2.52 mW. For this differential ring VCO, the figure of merit (FoM) is −122.821 dBc/Hz.
Persiya Gnana Golda D, S. Percy Deborah, Suji Sharon J., D.S. Shylu Sam, P. Sam Paul, D. Jayanthi, Ansia Liji K. S., and G. Nivetha
IEEE
Universal Asynchronous Receiver Transmitter is a serial communication protocol that helps in communicating data between devices. The verification of UART is important to eliminate any fault present in the design. In this paper UART module has been designed with transmitter UART and Receiver UART using System Verilog and the UVM based AHB Verification IP has been built to verify UART design. The coverage analysis block has been included in the test bench to analyze whether all the functionalities of the UART design has been verified. The functional coverage of 100% is achieved by using constrained random test with two test cases like half duplex communication mode an full duplex communication mode.
G. Sangeeth, D. Jayanthi, K. Kavitha, P. Ilanchezhian, and D. S. Shylu Sam
AIP Publishing
D. S. Shylu Sam, P. Sam Paul, Joel Samuel, and Vimukth John
World Scientific and Engineering Academy and Society (WSEAS)
Counters play an inevitable role in many VLSI circuits such as timers, frequency dividers, memories, and ADC/DAC. Integrating the timing discriminator, Pulse Swallow, and Correlated double sampling are various approaches used in counters for low power consumption. The main objective was to minimize the power consumption and device count. In this work, a new embedded clock gating technique is used in an 8-bit counter to reduce the switching activity. A clock gating circuit and clock buffer network pattern are used in the proposed algorithm to reduce the power consumption of synchronous counters. The proposed counter reduced the unwanted clock activity of all T FFs and noise is reduced to a greater extent thereby reducing the power and the device count. CMOS 45nm technology is used for designing the proposed counter 1.5 supply voltage. Simulated results show the improvement of the proposed approach over other conventional counters in terms of power consumption and device count.
D.S.Shylu Sam
Wydawnictwo SIGMA-NOT, sp. z.o.o.
S. Sarath, P.Sam Paul, G. Lawrance, and D.S.Shylu Sam
IEEE
A hybrid approach combining Artificial Neural Network (ANN) and Genetic Algorithm (GA) was proposed to optimize Magnetorheological Fluid (MRF) foam damper parameters for the maximum damping force. The hybrid approach improved the accuracy and efficiency of the prediction of damping force values, making it a valuable tool for designing and optimizing MRF foam dampers. The influence of each parameter for an optimized damper is studied and the values obtained using GA and ANN led to an increase in damping force. The study has significant implications for the design and evaluation of MR foam dampers for various applications, including vibration control and energy dissipation in structures.
Durai Balaji R, D.S. Shylu Sam, Manoj G, D. Jayanthi, Samson Immanuel J, Shaik Babafakruddin, and Shriashwinraja E G V
IEEE
The goal of this work is to design a half adder circuit for a multiplier with the considerations of low power dissipation and area reduction under the supply voltage of 1V. The novelty that is presented in this paper is the implementation of Pass Transistor Logic (PTL) technique to enhance the performance of adder logic. In comparison to previous studies, there has been a drastic reduction of transistors in terms of area, delay, and power. The proposed work reduces the power dissipation of the array multiplier. According to simulation results, the suggested design dissipates 1.105 $\\mu$W of power and 2.09 ns of delay for 10 transistors in half adder logic and 1.094 $\\mu$W of power and 2.14 ns of delay for 1S transistors in full adder logic. The proposed logic is designed and simulated in a 90 nm CMOS process.
Kanugula John Wesly, Sompalli Rajesh, Minnadivel Raj Rajeswaran, Muttaluru Aswartha Naidu, Ruby Grace, and D S. Shylu Sam
IEEE
To design a high-speed SqRt CSLA(Square Root Carry Select Look Ahead Adder) by using Multiplexer logic in order to reduce the number of gates. Performance comparison of proposed carry select adder with conventional CSLA is performed. SqRt CSLA architectures, including two hybrid designs, a high-speeddesign, and a design with the smallest area in comparison to prior CSLAs is proposed here. The first suggested architecture uses a new, quick add-one and multiplexing circuit to apply an optimized design of the BEC-based CSLA. The available CSLA, needs approximately the equal amount of area but uses significantly less energy and time. In this work a FAM CSLA using Transmission Gates (TG) based Full adder is proposed in 90nm Technology. Simulation results show that the delay of 11.50 ns is obtained which is less when compared with the conventional CSLA architectures.
E G V Shriashwinraja, J Samson Immanuel, G Manoj, K Aneesh, D S Shylu, Shaik Babafakruddin, and R Durai Balaji
IEEE
Data convertors are essential in any digital processing system. It is instrumental in acquiring sensor data in a meaningful way. For minimal power uses, an 8 bit Successive Approximation ADC is proposed in this work. It consumes 4. 55uW of power at a supply voltage of 0. S5V. The structure is realized using 90nm CMOS technology using cadence virtuoso. Low power consumption is attained by using SAR logic using d-flip flop and binary weighted capacitive DAC switching. A clock frequency of 2. 5M Hz and the sampling frequency of 20K Hz are being used for simulation purpose.
G. Cundaneswara Reddy, Ch. Nikhilesh Reddy, Vandana Bandi, M. Sreenivasulu, and D S Shylu
IEEE
This work proposes a new unidirectional latch based thermometer code shift registers as an alternative to conventional D flip-flops. The new design reduces the power consumed by the shift register. The research was conducted using a 45nm CMOS process and showed that the proposed shift registers consume $3.1 \\mu \\mathrm{W}$ and $6 \\mu \\mathrm{W}$ at a 100MHz clock frequency with VDD $=$ 1V. Compared to conventional unidirectional 4-bit shift registers, the proposed designs reduce power consumption by 90% and 84.6%, respectively. The paper’s author asserts that these new designs could offer significant advantages over traditional shift registers in terms of efficiency and performance.
Shaik Babafakruddin, G Manoj, J Samson Immanuel, D. S. Shylu Sam, R Durai Balaji, and V Shriashwinraja E G
IEEE
This article briefs on a low power 450 MHz a PLL-based frequency synthesizer for implantable medical devices (IMD). The technological devices inserted into human bodies to monitor and conduct medical diagnosis. Regular monitoring of normal functionality of the bodily physiological signals, such as hypertension, temperature, electrocardiograms, etc., is necessary for medical diagnoses. The charge pump circuit’s current mismatching problem is resolved and the frequency synthesizer’s power consumption is reduced by using a voltage-controlled LC oscillator with current reuse (CRVCO) and the cascaded gm boosting approach. At an output frequency of 450 MHz, the designed frequency synthesizer uses 0.223 mW of power. According to the test results, a 1. 2V supply voltage (VDD) corresponds to 0.45 mW/GHz is the Figure-of-merit (FOM)power.
K. Aneesh, G. Manoj, and S. Shylu Sam
World Scientific Pub Co Pte Ltd
In recent years, implantable biomedical devices like cardiac pacemaker, defibrillators, cochlear implants, visual prosthesis etc. have gained immense importance in the personal health monitoring system. Most of these devices are battery powered. The life span of a pacemaker is expected to be between 10 and 12 years. This shows the importance of having an ultra-low power design technique to improve the reliability and battery life of the system. To achieve this, power draws from the battery must be kept low. Analog-to-Digital Convertor (ADC) is a main block in the front-end sensing unit of an implant for measurements of various biophysiological signals. This is the most power consuming unit in the system. ADC alone consumes about 30%–35% of the total power. This work surveys various successive approximation ADC designs for biomedical signal acquisition, in terms of power consumption, signal to noise distortion ratio, sampling rate, resolution and Figure of Merit. The different switching schemes for capacitive DAC are also surveyed.
D.S.Shylu Sam, D. Jackuline Moni, P. Sam Paul, and D. Nirmal
Springer Science and Business Media LLC
S. Sarath, P. Sam Paul, D. S. Shylu, and G. Lawrance
ASTM International
Galle Sangeeth, D Jayanthi, Raji Krishna, P. Ilanchezhian, and D.S. Shylu Sam
IEEE
The main objective is to simulate Advanced interconnects used to connect System on Chip and identification of Malware present in the interconnects. The changed device-style incorporating test bench as a master driver is used. The versatile interconnect design is used for various types of bus transfers. Data bounding a secure transmission was achieved, as specified. The usage of verification module as a master will decrease the size of the circuit. The Malware inside the hardware is noticed whenever it was set off. This paper describes malware detection in Advanced- Micro-Controller- Bus-Architecture (AMBA) Advanced High-performance Bus (AHB) implementation is carried out by Verilog coding. In read/write operation the malware was implemented by simulator of Xilinx.
A J Herinsha, D.S. Shylu Sam, A Josephine Atchaya, and Mahendra Vignesh T
IEEE
This work is based on a low power comparator design for SAR ADCs. The pre-amplifier uses an inverter-based input pair with a floater reservoir capacitor to achieve both current reusing and dynamic bias. It also considerably lowers the impact of the operation corner and input common-mode voltage on comparison accuracy, offsets, and delays. This project has been worked with 45 nm technology and it gave the best results of the low power comparator.
A Josephine Atchaya, D.S. Shylu Sam, A J Herinsha, and Vignesh T Mahendra
IEEE
The design approaches for high-speed SAR ADCs are discussed in this work. It’s an interleaving architecture with a fast coarse successive approximation register quantizer and a two-way time-interleaved (TI) fine SAR analog to digital converter for the channel. A process by which successive-approximation analog to digital converters convert continuous analog waveforms into discrete digital representations by searching through all possible quantization levels before finally choosing a single output for each conversation. A system using interleaved sequential approximation register analog to digital converters may consume less power, cost, and be smaller than a system using pipeline analog to digital converters. The design has been implemented on90nm CMOS which has proven to the efficiently working with the supply voltage of 1.8V.
Rasna K B Das, S. Sridevi Sathya Priya, and D. Shylu
IEEE
Communication technologies such as wireless and optical fiber are vital components of today’s environment. As demand for increased data transfer and new technologies increases, novel research must be performed to combine the benefits of both technologies. In this case, optical communication technologies serve as the backbone of wireless technology. Currently, only a few studies have been conducted on Free Space Optical (FSO) communication employing Field Programmable Gate Arrays (FPGAs) and VerticalCavity SurfaceEmitting Lasers (VCSELs). When VCSEL is paired in conjunction with FPGA, there are only very few existing designs. These published researches cover many subjects yet are exceedingly complex and fragmented. The principal purpose of this Systematic Literature Review (SLR) is to identify the research trends and emerging themes in the development of FPGA-based Optical Hybrid Fiber - FSO Communication Systems. This review incorporates articles from prestigious journals that were indexed in scientific databases such as Science Direct, Shodh Ganga, IEEE Xplore, Google Scholar, and Scopus. This SLR exhibits the reliability and compatibility of FPGA-based FSOs when used with a lowcost optical source VerticalCavity SurfaceEmitting Laser Diode VCSEL), a range of technologies, communication methods, and approaches. This FPGA-based FSO is designed for optical communication applications that require highly secure transmission schemes, low radiation noise, a low bit error rate (BER), and increased data transfer rates. Additionally, VCSEL has a current threshold that is low, maximum conversion efficiency of power, and least consumption of power. Findings of this study can be used to direct future research in the area of hybrid Fiber-FSO optical communication systems development utilizing VCSEL and FPGA.